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Freescale Semiconductor /MKV56F24 /SIM /ADCOPT

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Interpret as ADCOPT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)ADC0TRGSEL 0 (0)ADC0PRETRGSEL 0 (00)ADC0ALTTRGEN 0 (0)HSADCIRCLK 0 (0)HSADCSTOPEN

HSADCIRCLK=0, ADC0TRGSEL=0000, ADC0PRETRGSEL=0, ADC0ALTTRGEN=00, HSADCSTOPEN=0

Description

ADC Additional Option Register

Fields

ADC0TRGSEL

ADC0 trigger select

0 (0000): PDB0 external trigger pin input (PDB0_EXTRG)

1 (0001): High speed comparator 0 output

2 (0010): High speed comparator 1 output

3 (0011): High speed comparator 2 output

4 (0100): PIT trigger 0

5 (0101): PIT trigger 1

6 (0110): PIT trigger 2

7 (0111): PIT trigger 3

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

11 (1011): FTM3 trigger

12 (1100): XBARA output 38

14 (1110): Low-power timer (LPTMR) trigger
ADC0PRETRGSEL

ADC0 pretrigger select

0 (0): Pre-trigger A

1 (1): Pre-trigger B
ADC0ALTTRGEN

ADC0 alternate trigger enable

0 (00): XBARA output 39.

1 (01): PDB0 channel1 trigger selected for ADC0

2 (10): PDB1 channel0 trigger selected for ADC0

3 (11): Alternate trigger selected for ADC0 as defined by ADC0TRGSEL.
HSADCIRCLK

HSADC Clock Status

0 (0): HSADC clock is Core/System clock.

1 (1): HSADC clock is MCGIRCLK.
HSADCSTOPEN

Enable HSADCs in STOP mode

0 (0): HSADCs stopsin system STOP modes

1 (1): HSADCs can be enabled in system STOP modes

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data